? semiconductor components industries, llc, 2005 august, 2005 ? rev. 9 1 publication order number: MC14541B/d MC14541B programmable timer the MC14541B programmable timer consists of a 16?stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power?on reset circuit, and output control logic. timing is initialized by turning on power, whereupon the power?on reset is enabled and initializes the counter, within the specified v dd range. with the power already on, an external reset pulse can be applied. upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external rc network. the 16?stage counter divides the oscillator frequency (f osc ) with the n th stage frequency being f osc /2 n . features ? available outputs 2 8 , 2 10 , 2 13 or 2 16 ? increments on positive edge clock transitions ? built?in low power rc oscillator ( 2% accuracy over temperature range and 20% supply and 3% over processing at < 10 khz) ? oscillator may be bypassed if external clock is available (apply external clock to pin 3) ? external master reset totally independent of automatic reset operation ? operates as 2 n frequency divider or single transition timer ? q/q select provides output logic level flexibility ? reset (auto or master) disables oscillator during resetting to provide no active power dissipation ? clock conditioning circuit permits operation with very slow clock rise and fall times ? automatic reset initializes all counters on power up ? supply voltage range = 3.0 vdc to 18 vdc with auto reset supply voltage range = disabled (pin 5 = v dd ) supply voltage range = 8.5 vdc to 18 vdc with auto reset supply voltage range = enabled (pin 5 = v ss ) ? pb?free packages are available* pin assignment nc = no connection 11 12 13 14 8 9 10 5 4 3 2 1 7 6 mode nc a b v dd q q/q sel nc r s c tc r tc v ss mr ar *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free indicator see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1 14 pdip?14 p suffix case 646 MC14541Bcp awlyywwg soic?14 d suffix case 751a tssop?14 dt suffix case 948g 1 14 14541bg awlyww 14 541b alyw 1 14 soeiaj?14 f suffix case 965 1 14 MC14541B alywg
MC14541B http://onsemi.com 2 maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range, (dc or transient) ?0.5 to v dd + 0.5 v i in input current (dc or transient) 10 (per pin) ma i out output current (dc or transient) 45 (per pin) ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature, (8?second soldering) 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, prec autions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operat ion, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. ordering information device package shipping ? MC14541Bcp pdip?14 500 units / rail MC14541Bcpg pdip?14 (pb?free) 500 units / rail MC14541Bd soic?14 55 units / rail MC14541Bdg soic?14 (pb?free) 55 units / rail MC14541Bdr2 soic?14 2500 units / tape & reel MC14541Bdr2g soic?14 (pb?free) 2500 units / tape & reel MC14541Bdtr2 tssop?14* 2500 units / tape & reel MC14541Bf soeiaj?14 50 units / rail MC14541Bfel soeiaj?14 2000 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
MC14541B http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 10 15 ? 7.96 ? 4.19 ? 16.3 ? ? ? ? 6.42 ? 3.38 ? 13.2 ? 12.83 ? 6.75 ? 26.33 ? ? ? ? 4.49 ? 2.37 ? 9.24 ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 1.93 4.96 19.3 ? ? ? 1.56 4.0 15.6 3.12 8.0 31.2 ? ? ? 1.09 2.8 10.9 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (pin 5 is high) auto reset disabled i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc auto reset quiescent current (pin 5 is low) i ddr 10 15 ? ? 250 500 ? ? 30 82 250 500 ? ? 1500 2000 adc supply current (notes 3 & 4) (dynamic plus quiescent) i d 5.0 10 15 i d = (0.4 a/khz) f + i dd i d = (0.8 a/khz) f + i dd i d = (1.2 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. when using the on chip oscillator the total supply current (in adc) becomes: i t = i d + 2 c tc v dd f x 10 ?3 where i d is in a, c tc is in pf, v dd in volts dc, and f in khz. (see fig. 3) dissipation during power?on with automatic reset enabled is typically 50 a @ v dd = 10 vdc.
MC14541B http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (note 6) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay, clock to q (2 8 output) t plh , t phl = (1.7 ns/pf) c l + 3415 ns t plh , t phl = (0.66 ns/pf) c l + 1217 ns t plh , t phl = (0.5 ns/pf) c l + 875 ns t plh t phl 5.0 10 15 ? ? ? 3.5 1.25 0.9 10.5 3.8 2.9 s propagation delay, clock to q (2 16 output) t phl , t plh = (1.7 ns/pf) c l + 5915 ns t phl , t plh = (0.66 ns/pf) c l + 3467 ns t phl , t plh = (0.5 ns/pf) c l + 2475 ns t phl t plh 5.0 10 15 ? ? ? 6.0 3.5 2.5 18 10 7.5 s clock pulse width t wh(cl) 5.0 10 15 900 300 225 300 100 85 ? ? ? ns clock pulse frequency (50% duty cycle) f cl 5.0 10 15 ? ? ? 1.5 4.0 6.0 0.75 2.0 3.0 mhz mr pulse width t wh(r) 5.0 10 15 900 300 225 300 100 85 ? ? ? ns master reset removal time t rem 5.0 10 15 420 200 200 210 100 100 ? ? ? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. figure 1. power dissipation test circuit and waveform figure 2. switching time test circuit and waveforms pulse generator v dd c l q r s ar q/q select mode a b mr v ss 20 ns 20 ns 90% 50% 10% 50% duty cycle (r tc and c tc outputs are left open) pulse generator v dd r s ar q/q select mode a b mr v ss c l q 20 ns 90% 50% 20 ns 10% r s q t plh 50% 90% 50% 10% 50% t tlh t thl t phl
MC14541B http://onsemi.com 5 expanded block diagram a12 b13 r tc 1 c tc 2 r s 3 5 auto reset osc reset c 2 8 8?stage counter reset power?on reset 6 master reset 2 10 2 13 2 16 c 8?stage counter reset 1 of 4 mux 10 mode 9 q/q select 8q v dd = pin 14 v ss = pin 7 frequency selection table a b number of counter stages n count 2 n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 truth table pin state 0 1 auto reset, 5 auto reset operating auto reset disabled master reset, 6 timer operational master reset on q/q ,9 output initially low after reset output initially high after reset mode, 10 single cycle mode recycle mode figure 3. oscillator circuit using rc configuration 3 r s r tc c tc 21 to clock circuit internal reset
MC14541B http://onsemi.com 6 typical rc oscillator characteristics figure 4. rc oscillator stability figure 5. rc oscillator frequency as a function of r tc and c tc 8.0 4.0 0 ?4.0 ?8.0 ?12 ?16 125 100 75 50 25 0 ?25 ?55 t a , ambient temperature ( c) frequency deviation (%) v dd = 15 v 10 v 5.0 v r s = 0, f = 10.15 khz @ v dd = 10 v, t a = 25 c r s = 120 k , f = 7.8 khz @ v dd = 10 v, t a = 25 c r tc = 56 k , c = 1000 pf 100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 1.0 k 10 k 100 k 1.0 m f, oscillator frequency (khz) r tc , resistance (ohms) 0.0001 0.001 0.01 0.1 c, capacitance ( f) v dd = 10 v f as a function of r tc (c = 1000 pf) (r s 2r tc ) f as a function of c (r tc = 56 k ) (r s = 120 k ) operating characteristics with auto reset pin set to a ?0? the counter circuit is initialized by turning on power. or with power already on, the counter circuit is reset when the master reset pin is set to a ?1?. both types of reset will result in synchronously resetting all counter stages independent of counter state. auto reset pin when set to a ?1? provides a low power operation. the rc oscillator as shown in figure 3 will oscillate with a frequency determined by the external rc network i.e., if (1 khz f 100 khz) 2.3 r tc c tc 1 f = and r s 2 r tc where r s 10 k the time select inputs (a and b) provide a two?bit address to output any one of four counter stages (2 8 , 2 10 , 2 13 and 2 16 ). the 2 n counts as shown in the frequency selection table represents the q output of the n th stage of the counter. when a is ?1?, 2 16 is selected for both states of b. however, when b is ?0?, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). the q/q select output control pin provides for a choice of output level. when the counter is in a reset condition and q/q select pin is set to a ?0? the q output is a ?0?, correspondingly when q/q select pin is set to a ?1? the q output is a ?1?. when the mode control pin is set to a ?1?, the selected count is continually transmitted to the output. but, with mode pin ?0? and after a reset condition the r s flip?flop (see expanded block diagram) resets, counting commences, and after 2 n?1 counts the r s flip?flop sets which causes the output to change state. hence, after another 2 n?1 counts the output will not change. thus, a master reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. digital timer application r tc c tc nc r s ar mr input t mr v dd b a n.c. output v dd mode q/q t + t mr 1 2 3 4 5 6 78 9 10 11 12 13 14 when master reset (mr) receives a positive pulse, the internal counters and latch are reset. the q output goes high and remains high until the selected (via a and b) number of clock pulses are counted, the q output then goes low and remains low until another input pulse is received. this ?one shot? is fully retriggerable and as accurate as the input frequency. an external clock can be used (pin 3 is the clock input, pins 1 and 2 are outputs) if additional accuracy is needed. notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time q output will be high.
MC14541B http://onsemi.com 7 package dimensions pdip?14 p suffix case 646?06 issue n 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ?t? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
MC14541B http://onsemi.com 8 package dimensions tssop?14 dt suffix case 948g?01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n
MC14541B http://onsemi.com 9 package dimensions soeiaj?14 f suffix case 965?01 issue o h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 1.42 ??? 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1 dimensioning and tolerancing per ansi y14.5m, 1982. 2 controlling dimension: millimeter. 3 dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4 terminal numbers are shown for reference only. 5 the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z
MC14541B http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC14541B/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
|
